Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum and so, is considered as a viable alternative for metallization patterns, particularly for integrated circuits with smaller features. However copper has a high mobility and can diffuse easily through the interlayer dielectric materials, such as low-k or ultra low k dielectrics, commonly used in integrated circuits. This diffusion or drift of copper through the various layers can cause degradation in the performance of the device. In addition under the influence of current flow, copper migrates within the metallization and vias creating voids and dendrites when the Blech length is exceeded.
Consequently, a diffusion barrier layer that has a high thermal stability, low resistivity and a low copper diffusion constant is used to overcome the diffusion and electromigration problems. Traditionally, some of the diffusion barrier materials used are tantalum nitride (TaN), tantalum (Ta) and titanium nitride (TiN) which are deposited using conventional deposition processes such as physical vapor deposition (PVD) process, chemical vapor deposition (CVD) and atomic layer deposition (ALD). The thickness of the diffusion barrier layer over the interlayer dielectric must be sufficient to limit the diffusion of copper into the surrounding inter layer dielectric materials and over the metallization must be sufficient to eliminate the critical electromigration effect.
Accordingly, a need exists for a process to modulate the thickness of deposition of a barrier layer on the walls and floor of recessed feature.